Modern ultra large-scale integrated circuit (ULSI) chips incorporate large numbers of SRAM cache tag memories that enhance the speed of systems using the chips. The physical size of the cells that make up the SRAM cache tag memories often determines the density and performance of the chips. As such, smaller, more SRAM dense cache tag memories exhibit better performance characteristics. The most effective method to achieve a small cell for a SRAM cache tag memory is to shorten the distance of the interconnecting wire between the input and output nodes of the opposite inverters of the flip-flop making up the cell. Such short and compact connection layouts are generally termed "local interconnects." There are three known methods often used to form local interconnects for ULSI chip applications. They are (1) forming directly-reacted titanium nitride (TiN) local interconnects during the normal titanium silicidation portion of the integrated circuit fabrication process, (2) forming a silicide local interconnect by depositing and patterning a composite material, and (3) forming a local interconnect with a buried contact.
In the directly-reacted method for forming a TiN local interconnect, a titanium layer is deposited on the semiconductor device and then heated. During the heat process, titanium in contact with the moat areas of the device forms a bilayer of titanium silicide covered with titanium nitride. Titanium in contact with oxide regions of the device forms titanium nitride. A titanium nitride film is retained to form the local interconnect through a combination of wet chemical and dry plasma etch steps with a photoresist pattern. While this process is simple, it suffers from poor manufacturing yield. This is because the dry plasma etch step of the process in which the titanium nitride is removed does not have enough selectivity to the titanium silicide areas to avoid some undesirable etching of the titanium silicide moat and polysilicon regions of the device. The lack of sufficient selectivity requires that the etch time be kept short. Even so, the low selectivity of the dry plasma etch step thins the titanium silicide on the moat and polysilicon areas of the device.
Because no vigorous full strength wet chemical etch can be used to remove the titanium nitride from undesired areas, it is inevitable that some conductive titanium nitride or titanium oxide compounds can be left which can electrically connect minimum spaced active areas that should be electrically isolated. To minimize this possibility, the titanium deposition thickness and resulting titanium nitride thickness must be limited. Additionally, to remove the residual titanium nitride filament material from sidewall oxide edges, it is necessary to perform a wet chemical etch with a mixture of diluted ammonium hydroxide and hydrogen peroxide in a sonic environment.
The wet etch is a messy and time-consuming step, which, if it were possible to avoid, could significantly increase local interconnect formation process throughput. Additionally, the sonic energy and filament's tenacity, often leave no margin for the photoresist to work. This often results in a total loss of the desired local interconnect features due to lifting photoresist. To alleviate to some extent this photoresist adherence problem, it is necessary to separate the wet etch into two steps in which the photoresist is stripped after the first etch and re-patterned and the etch completed. This adds another lithographic patterning step (so called double patterning) which further complicates the process.
in forming a silicide local interconnect (i.e., the second often-used method), composite material is deposited and patterned to form a silicided local interconnect. The most commonly used silicide materials are tungsten and titanium. By mixing tungsten and titanium with a sputtered silicon layer, this process forms a conductive silicide local interconnect. Sputtered silicon is necessary to prevent junction spiking during the silicidation process. Sputtered titanium nitride may be used by itself for such an application. This approach, however, suffers from the same low selectivity problems that plague the dry etch of directly-reacted titanium nitride local interconnect process and poses the same filament problem of that process. As such, mass production using the silicide local interconnect has limited potential.
The third known method to form an integrated circuit local interconnect is to form a local interconnect with a buried contact. In this method, a layer of oxide is deposited and contact holes are defined prior to the local interconnect material deposition. Having this oxide layer may overcome the dry etch low selectivity problem. However, the step of making the buried contact adds significantly to fabrication costs and limits the chip design size. This is due to the required alignment tolerances between the buried contact and moat and the buried contact and the local interconnect.
Accordingly, there is a need for a method to form a local interconnect for integrated circuit applications such as ULSI circuit chips that avoids thinning of the titanium silicide in the moat and polysilicon regions due to a low selectivity dry plasma etch step necessary to form the local interconnect.
There is a need for a method that avoids the requirement to wet etch the structure associated with the local interconnect following the dry plasma etch step of the local interconnect forming process.
There is a need for a method of forming a local interconnect for an integrated circuit that does not impose limitations on the local interconnect material layer thickness.
There is a further need for a method of forming a local interconnect for an integrated circuit that avoids the double patterning process of conventional local interconnect forming methods.
There is yet the need for a method that permits use of a full strength wet strip process following the formation of the local interconnect.